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Chapter 3: Hardware Description
R
SAMTEC Mezzanine Expansion Card Support
The ML555 board supports the addition of mezzanine boards attached to connectors P32
and P33. 5V DC power is provided to the mezzanine board on connector P48 (see
Table 3-14 ). A serial configuration interface is provided on connector P47 (see Table 3-15 ).
The P47 interface is connected to FPGA Bank 1 with a V CCO reference voltage of 2.5V.
Figure 3-5, page 45 shows the P47 and P48 mezzanine connectors.
Table 3-14:
Connector P48 Pinout
Connector Pin
Pin 1
Pin 2
Signal
+5V
GROUND
Table 3-15:
Connector P47 Pinout
Connector Pin
Pin 1
Pin 2
Pin 3
Pin 4
Signal
EXT_SEN
EXT_SDATA
EXT_SCLK
EXT_RESET
FPGA Pin
K14
L14
H22
G22
Universal Serial Bus Port
The ML555 board provides a connector (P1) for a Universal Serial Bus (USB) port. A USB to
RS-232 converter module is provided on the board. The FPGA connection uses standard
UART interface protocols, while the external interface is USB 2.0. Device drivers are
provided on the reference CD to enable a Microsoft Windows or Linux operating system
personal computer to emulate a serial port.
The board uses the Maxim MAX3008EUP (U4) device to convert the RD, TD, RTS, and CTS
signals from 3.3V (CP2102 side) to 2.5V (FPGA side) of the interface. The MAX3008 RS-232
interface device operates from a 2.5V supply. The interface between the MAX3008 and the
FPGA is at LVCMOS_25 standard levels. The user must provide a UART core internal to
the FPGA to enable serial communication between the FPGA and USB attached serial port.
UART cores are available from the Xilinx IP center at www.xilinx.com/ipcenter .
Table 3-16 describes the RS-232 interface pin assignments.
Table 3-16:
RS-232 Interface Signal Names and Pin Assignments
Signal Name
USB_RX
USB_TX
USB_RTS_B
USB_CTS_B
USB_DSR_B
USB_DTR_B
FPGA In/Out
Out
In
In
Out
Out
In
Description
USB Receive Data (FPGA UART Transmit port)
USB Transmit Data (FPGA UART Receive port)
USB Request to Send
USB Clear to Send
USB Data Set Ready
USB Data Terminal Ready
FPGA Pin Number (1)
K21
L20
L21
J22
K16
L15
50
www.xilinx.com
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
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